The present invention relates to the integration of pin-mounted components, such as ordinary DIP packages, with various base elements to form integrated electronic systems. One form of base element is a multi-chip electronic module having a plurality of integrated circuit chips and other components electrically interconnected in a high density interconnect (HDI) structure.
As disclosed in Eichelberger et al. U.S. Pat. No. 4,783,695, and related patents such as those referenced hereinbelow, a high density interconnect structure as developed by General Electric Company offers many advantages in the compact assembly of digital and other electronic systems. For example, an electronic system such as a microcomputer which incorporates between thirty and fifty chips, or even more, can be fully assembled and interconnected on a single substrate which is two inches long by two inches wide by 50 mils thick. This structure is referred to herein as an "HDI structure", and the various previously-disclosed methods for fabricating it are referred to herein as "HDI fabrication techniques".
Briefly, this high density interconnect structure employs, a ceramic substrate which may be made of alumina, for example, with a thickness between 25 and 100 mils. The substrate is of appropriate size and strength for the overall electronic system in which it is utilized. This size is typically on the order of two inches square.
Individual cavities, or one large cavity having appropriate depths at the intended locations of the various chips, are prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, laser or ultrasonic milling is used to form the cavities in which the various chips and other components are subsequently positioned. For systems where it is desired to place chips of uniform size edge-to-edge, a single large cavity may be satisfactory.
The various components are placed in their desired locations within the cavities and adhered by means of a thermoplastic adhesive layer, preferably Ultem.RTM. polyetherimide resin available from General Electric Company, Pittsfield, Mass. Thus the structure is a "chips first" structure. More particularly, the entire structure is heated to the softening point of the Ultem polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C. depending on the formulation used) and then cooled to thermoplastically bond the individual components to the substrate. At this stage, the upper surfaces of all components and the substrate are disposed in substantially a common plane.
A multi-layer interconnect overcoat structure is then built up to electrically interconnect the components into an actual functioning system. To begin the HDI overcoat structure, a polyimide dielectric film, which may be Kapton.RTM. polyimide, about 0.0005 to 0.003 inch (12.5 to 75 microns) thick and available from E. I. du Pont de Nemours & Company, Wilmington, Del., is pretreated to promote adhesion and coated on one side with Ultem polyetherimide resin or another thermoplastic and laminated across the top of the chips, other components and the substrate, with the Ultem resin serving as a thermoplastic adhesive to hold the Kapton film in place.
The actual as-placed locations of the various components and contact pads thereon are determined, and via holes are adaptively laser drilled in the Kapton film and Ultem adhesive layers in alignment with the contact pads on the electronic components. Exemplary laser drilling techniques are disclosed in Eichelberger et al. U.S. Pat. Nos. 4,714,516 and 4,894,115; and in Loughran et al. U.S. Pat. No. 4,764,485.
A metallization layer is deposited over the Kapton film layer and extends into the via holes to make electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it, or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser which is scanned relative to the substrate to provide an accurately aligned conductor pattern at the end of the process. Exemplary techniques for patterning the metallization layer are disclosed in Wojnarowski et al. U.S. Pat. Nos. 4,780,177 and 4,842,677; and in Eichelberger et al. U.S. Pat. No. 4,835,704 which discloses an "Adaptive Lithography System to Provide High Density Interconnect". Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system as disclosed in U.S. Pat. No. 4,835,704.
Additional dielectric and metallization layers are provided as required in order to make all of the desired electrical connections among the chips.
The ability to extend into the third dimension is highly desirable in electronics, especially multichip module electronics. Thus, commonly-assigned Wojnarowski et al. allowed application Ser. No. 07/504,749, filed Apr. 5, 1990 entitled "High Density Interconnect Structure With Top-Mounted Components" discloses a configuration where the functionality, versatility, connection and packing density of a multi-chip module high density interconnect structure are enhanced by mounting one or more components on top of the high density interconnect structure and connecting these top-mounted components in various ways to conductors of the high density interconnect structure and the chips embedded therein.
The techniques disclosed in Ser. No. 07/504,749 are not, however, particularly suitable for use in combination with pin-mounted components such as standard DIP (Dual In-Line Pins) packages, magnetic toroids, memory cube devices and other pin-mounted components. As another example, programmable devices such as EPROMS (Erasable, Programmable, Read Only Memories) and various programmable logic devices are commonly available in DIP packages, and could be readily used in combination with HDI structures if a suitable interconnection technique were known. Of particular interest are memory cubes such as those made by Texas Instruments and by Irvine Sensors. Such memory cubes typically have pins which are ten to twenty mils in length and spaced approximately twenty to twenty-five mils center-to-center in a rectangular array of 240 pins having an overall size of 0.567 inch long by 0.172 inches wide.
These pin-mounted components could be potted and lapped, and then incorporated into an HDI structure at the same time as semiconductor chips are mounted (but in cavities deeper compared to the usual HDI process). However, the cost would be relatively high, and there are numerous practical difficulties related to potting, pin alignment, and pad out interfaces. For example, in the case of memory cubes, variation in lead positioning within the cube, and cube-to-cube variations, are incompatible with micron HDI dimensioning, even when the adaptive lithography techniques are employed.
Thus it remains desirable to mount the pin-mounted components on top of an HDI structure. It would further be desirable to make mass memory modules with high cube-to-cube packing density in a manner which is cost effective, mechanically sound, repairable and reliable. Conceptually, interconnect pads could be provided on top of the HDI structure, and the pins of the pin-mounted components somehow attached and electrically connected, somewhat in the manner as is done in the case of conventional surface mount technology.
Interconnections between metal surfaces that mate together can be accomplished only in a limited number of ways. Soldering, conductive gluing, vacuum metal deposition, and welding are some of these ways.
Vacuum metal deposition techniques used in the present HDI process cannot be used to interconnect bottom pinout devices, since the metal deposition will not form an adequate connection with pins that are undershadowed by the part in this manner.
Soldering would be a possibility. However, the HDI process at present is not readily compatible with 200.degree.-260.degree. C. soldering temperatures, due to the limitations of the interlayer adhesives. Additionally, surface bonding of pins to interconnect pads is not practical when employing wave soldering. Further, solder "wicks up" or flows readily into regions of the memory cubes intended to be solder-free when the cubes are processed at temperatures greater than 195.degree.-200.degree. C. Still further, the application and removal of solder fluxes are difficult. Thus, soldering arrays of pins of pin-mounted components to pads is a near impossibility, and would result in extremely low yields.
Another consideration is that memory cubes have pins protruding outward which are not controlled to a tight tolerance; that is they experience random overall runout from one end to the other, as well as skew from row to row. To adapt to HDI processes as previously practiced would require a direct measurement of each memory cube and adjustment of the artwork for each. This is highly undesirable, due to the measurement times involved. To interface these two technologies would require an exact measurement and placement and surface bonding. HDI has some height variations from chip to chip and does not lend itself to use of absolutely flat mounting surfaces of each pin within the memory cube array.
In short, the application of surface mount solders and/or glues and to perfectly align hundreds, to many thousands of small pads, with variable length pins, protruding out of the memory cubes becomes statistically very difficult. The solders and glues melt and move, making connections unreliable and blind joint inspection impossible.
The above-identified related application Ser. No. 07/904,930 discloses an electronic system which integrates a base element with a pin-mounted component. As disclosed in that application, the base element has a generally planar boundary with interconnect pads on the boundary. As one example, the base element may comprise a high density interconnect (HDI) assembly including a substrate with at least one cavity, a plurality of electronic components disposed within the cavity and having contacts thereon, and a multilayer interconnect structure overlying and bonded to the electronic components and interconnecting selected ones of the component contact pads. The multilayer interconnect structure includes interleaved layers of dielectric material and conductive material, and an upper portion of the multilayer interconnect structure comprises the planar boundary having interconnect pads thereon. As another example, the base element may comprise a printed circuit board or other substrate, with or without a multilayer interconnect structure.
In the method disclosed in Ser. No. 07/904,930 for integrating a pin-mounted component and a base element, a polymer mask layer is applied to the base element surface, also referred to herein as the base element planar boundary. The polymer mask layer thickness is within the approximate range of two to ten mils, and may be applied by adhesively bonding a sheet of polymer material to the base element. A spin-on or spray-on glue may be applied to the base element or to the mask layer directly, then dried, and the mask layer bonded to the base element.
Next, well-like via holes are formed in the polymer mask layer over the interconnect pads, extending to and exposing at least portions of the interconnect pads, enabling electrical connections thereto. The preferred method for forming the well-like via holes is laser dithering, such as disclosed in Eichelberger et al. U.S. Pat. No. 4,894,115. Preferably, the holes are formed of sufficient size to accommodate runout tolerances in the locations of the connection pins of the pin-mounted component; alternatively, however, the positions of the connection pins may be determined in advance, and the holes adaptively positioned to correspond therewith.
Uncured polymer material is then put into the holes. In the method of Ser. No. 07/904,930, the uncured polymer material may comprise an epoxy loaded with silver particles, also referred to herein as "silver-loaded epoxy". The conductive polymer material is also referred to as conductive bonding glue. In some applications, however, only attachment is required, and non-conductive epoxy is employed. In either event, the uncured polymer material is put into the holes by a process such as squeegee flood stroke filling, or by metering a controlled amount of uncured polymer material into the holes using available pick-and-place glue placement equipment. To aid in leveling and flow-out of the uncured polymer material, heat may be applied to warm the assembly, while maintaining the assembly below cure temperature.
Finally, the pins of the pin-mounted component are cleaned (e.g. alcohol wash and dry) and inserted into the via holes, and the conductive polymer material is cured.
The well-like via holes serve several functions. One function is to provide a "well" to hold a sufficient quantity of conductive bonding glue surrounding the individual pins in excess of the quantity which would surround individual pins merely glued to a pad, while confining the conductive glue so that short circuits do not occur. Another function of the well-like via holes is to provide mechanical rigidity and positive positioning, and at the same time accommodate runout and short pin situations. The resultant assembly is structurally more secure than, for example, assemblies made employing conventional surface mount technology. Further, as described in Ser. No. 07/904,930, the structure is repairable. In selecting for use the method of Ser. No. 07/904,930, an important consideration is the difficulty in putting precise quantities of uncured silver-epoxy material in the well-like via holes using existing epoxy paste delivery systems.